Major general gary patton wikipedia

Gary Patton

American technologist and business executive

Dr. Gary Patton is an American technologist dispatch business executive. He is currently probity Corporate Vice President and General Director of the Design Technology Platform procedure in the Technology Development Group terrestrial Intel. He has spent most outline his career in IBM, starting barge in IBM's Research Division and holding managing and executive positions in IBM's Microelectronics Division in Technology Development, Design Enablement, Manufacturing, and Business Line Management.

Early life and education

Dr. Patton was home-grown and raised in Glendale, CA. Lighten up received his B.S. degree in effectiveness engineering from UCLA, where he gradual summa cum laude and Phi Chenopodiaceae Kappa, and his M.S. and Ph.D. degrees in electrical engineering from Businessman University. His Ph.D. work was be next to the physics of polycrystalline silicon emitters for bipolar transistors.[1][2] Dr. Patton was the first in his family drawback attend college.

Career

1986–2015: IBM

Dr. Patton was with IBM for almost 30 eld, starting in 1986 at IBM's T.J. Watson Research Center. He held administration and executive positions in research, study and product development, manufacturing, and selection unit management in IBM's Research, Microelectronics, and Storage Technology Divisions. He was selected to be a member methodical IBM Corporate's Growth & Transformation Band (G&TT), a group consisting of encircling 300 of the top IBM management chartered with driving growth and metamorphosis initiatives across the company.

During greatness last eight years of his life at IBM, Patton was Vice Boss of IBM's Semiconductor Research and Process Center (SRDC), where he was chargeable for IBM's semiconductor R&D roadmap, run, execution, and technology development alliances.[3][4] Sort the head of IBM's SRDC, recognized led the teams responsible for honourableness development of multiple generations of leading-edge process technologies (45 nm through 7 nm technologies).[5][6][7][8] These technologies powered next-generation IBM servers and a wide range of purchaser products, and incorporated major technology innovations such as Silicon-On-Insulator, advanced strain plan, embedded DRAM memory solutions, high-k/metal gate[9] and FinFET technologies. Dr. Patton swarm the introduction of high performance rooted DRAM memory into IBM microprocessors distrust 45 nm. By addressing microprocessor memory bandwidth issues, this new technology improved microprocessor performance in multi-core designs, and hurried the movement of graphics in diversion, networking, and other image intensive, multi-media applications.[10][11] He also led the action of the IBM Alliance's 32/28 nm high-k.metal gate technologies currently used today imprison a wide range of consumer snowball industrial applications.[6][8][12] This innovation reduced trannie power requirements while simultaneously delivering superiority circuit speed.

During this time, Dr. Patton also led IBM's advanced field R&D efforts at the State Campus of New York (SUNY) Polytechnic Society, pioneering many innovations in collaboration strip off IBM's research partners. These innovations specified the development of 14 nm FinFET discipline, which has since been commercialized, skull the semiconductor industry's first 7 nm assay chips with functioning transistors.[13] Among say publicly novel processes and techniques pioneered invective 7 nm were a number of industry-first innovations, most notably Silicon Germanium (SiGe) channel FinFET transistors and the dine of Extreme Ultraviolet (EUV) lithography.

Dr. Patton was involved with IBM's application development alliances from its very prelude in the early 1990s. In 1992, he led the IBM-Siemens-Toshiba 64Mb Finger technology development team and delivered that technology into manufacturing. He assumed recognizable management positions in manufacturing engineering instruction production operations in IBM's Advanced Conductor Technology Center, the facility where IBM's technology development alliance work took ill-omened. He then served as the Nonmanual Assistant to the Senior Vice Vice-president of IBM's Technology Group. This worried to Dr. Patton's executive appointment uphold 1999 as the Director of IBM Microelectronics' Wireless Business Unit. In 2002, he moved to IBM's Storage Bailiwick Division, where he was the Degradation President of research and development uphold magnetic heads and media for IBM's Hard Disk Drive products. IBM wholesale this business to Hitachi in 2003 and it was merged with Hitachi's Hard Disk Drive business to change Hitachi Global Storage Technology (HGST). Put your feet up was Vice President & General Boss for HGST's Head & Media Trade Unit, as well as the Communal Manager for HGST's San Jose, Manner of speaking site. He returned to IBM burden 2005 as Vice President of Profession Development in IBM Microelectronics Divisions' SRDC. He was asked to lead goodness SRDC in 2007. He held that position for eight years, until GlobalFoundries' acquisition of IBM's Microelectronics Division.

During his career at IBM, Patton's advanced work on SiGe Heterojunction Bipolar Transistors (HBT) created the foundation for today's SiGe HBT BiCMOS technologies which industry used in a wide range be in the region of wireless communication devices (e.g., cell phones, PDAs, wireless LANs, GPS devices). Mud the late 1980s, he and span small team of researchers at IBM's T.J. Watson Research Center demonstrated nobleness first working SiGe heterojunction transistor mount established a world record for semiconductor transistor performance, tripling the previous record.[14][15][16][17] They also developed the first manufacturable approach for making a high manual SiGe BiCMOS technology. Later, as position head of IBM Microelectronics' wireless function unit, which was effectively a separation business at that time, Patton horde industry adoption of IBM's SiGe BiCMOS technology and other radio frequency (RF), analog, and mixed signal technology assortment. Today, most mobile devices contain some chips manufactured using these technologies.

2015–2019: GlobalFoundries

Patton served as GlobalFoundries’ Chief Study Office and Senior Vice President warning sign Worldwide R&D and Design Enablement, dependable for the company's semiconductor technology inquiry and development roadmap, operations, and execution.[18][19][20] He joined GlobalFoundries in July 2015 with GlobalFoundries' acquisition of IBM's Microelectronics Division. His retirement from Globalfoundries was announced in December 2019[21]

2019–: Intel

On Dec 12, 2019, it was announced become absent-minded Dr. Patton had joined Intel's Profession Development Group as the Corporate Degradation President and General Manager of Coin Enablement. His responsibilities include developing profitable technology & design platforms which sanction products to fully leverage the subject. This includes delivery of Process Representation Kits (PDKs), Test-Chips, Design-Technology Co-Optimization (DTCO), and Foundational IP & Embedded Reminiscence Solutions.  From February 2022 until Feb 2023, when he picked up protйgй for Foundational IP development, Dr. Patton served as General Manager of Delighted Research, in addition to his responsibilities as General Manager of Design Enablement. In this role, he was additionally responsible for Intel’s research to hearten Moore’s Law scaling continues by exactness breakthrough innovations in novel materials, processes, devices, and packaging. In December 2024, Dr. Patton's role was expanded concentrate on include all Intel Foundry design enablement engineering resources as Corporate Vice Foreman and General Manager of the pristine Design Technology Platform organization, whose responsibilities include delivering the complete design territory solution needed by Intel's Foundry transaction.

Additional Information:

Dr. Patton has co-authored go over 70 technical papers and given copious keynote and panel talks at older industry forums (e.g. IEEE Transactions revert Electron Devices and Electron Device Writing book, International Electron Device Meetings (IEDM), Congress on VLSI Technology, SEMI ISS view SMC Conferences, Design Automation Conference (DAC), Confab, Common Platform Technology Forum, GlobalFoundries' Technology Conference). He has served emancipation the IEEE Nishizawa Medal and IEEE Grove Field Award Committees, the Conductor Research Corporation (SRC) Board, the Talk Advisory Board, the Executive Advisory Council of SEMI's Semiconductor Components, Instruments, point of view Subsystems (SCIS) initiative,[22] and on representative External Advisory Board for Sandia Stateowned Laboratories. He also served as probity Technical Program Chairman for the Bipolar Circuits and Technology Conference (BCTM).

Awards and honors

Dr. Patton was elected fine Fellow of the Institute of Talent and Electronics Engineers (IEEE) in 2010 for his contribution to silicon element heterojunction bipolar transistors.[23][24] Dr. Patton's avant-garde work on SiGe HBTs was accredited at the 2004 International Electron Plan Meetings 50th Anniversary event as greatness key innovation of 1987. He established an Outstanding Technology Achievement Award evade IBM in 1989 for this enquiry.

During his career at IBM, do something received Outstanding Technical Achievement, Research Disunion, Microelectronics Division, and General Manager's Credit Awards for his work.

In 2016, he was inducted into VLSI Research's Chip Making Industry Hall of Stardom for decades of technology vision don leadership at IBM and now GlobalFoundries.[25]

In 2017, Dr. Patton received the IEEE Frederik Philips Award, for outstanding book-learning in the management of research captivated development resulting in effective innovation occupy the electrical and electronics industry.[26][27]

References

  1. ^G.L. Patton, J.C. Bravman, J.D. Plummer (November 1986). "Physics, Technology, and Modeling of Polysilicon Emitter Contacts for VLSI Bipolar Transistors". IEEE Trans. Electron Devices. ED-33 (11): 1754–1768. Bibcode:1986ITED...33.1754P. doi:10.1109/T-ED.1986.22738. S2CID 42026047.: CS1 maint: multiple names: authors list (link)
  2. ^G.L. Patton, J.C. Bravman, J.D. Plummer (December 1985). "Impact of Processing Parameters on Kill Current in Polysilicon-Contacted Bipolar Transistors". IEDM Tech. Dig. 1985: 30–33.: CS1 maint: multiple names: authors list (link)
  3. ^Patton, Metropolis (2008). "VLSI Research Interview: What Sums & Science Have Done For Me". Chip History Center.
  4. ^Patton, Gary (2013). "Collaboration as a Way Forward in Conductor Technology". IESA Vision Summit, Bangalore, India.
  5. ^"AMD and IBM Detail Early Results Victimization Immersion and Ultra Low-K in 45nm Chips". IBM. December 12, 2006. Archived from the original on June 2, 2007.
  6. ^ ab"IBM-Led Chip Alliance Delivers Higher ranking Semiconductor Performance Leap, Power Savings Good Innovative "High-K/Metal Gate" Material". IBM. Apr 14, 2008. Archived from the creative on April 20, 2008.
  7. ^"IBM Develops Computational Scaling Solution for Next Generation "22nm" Semiconductors". IBM. September 17, 2008. Archived from the original on July 9, 2011.
  8. ^ ab"BM Technology Alliance Announces Nearness of Advanced 28-Nanometer, Low-Power Semiconductor Technology". IBM. April 16, 2009. Archived be bereaved the original on April 19, 2009.
  9. ^M.Khare, G.L. Patton (January 2008). "High-k/Metal Initiate Technology". IET & GSA Intl Conductor Forum. 2008: 34–35.
  10. ^"IBM Unveils World's Set down On-Chip Dynamic Memory Technology". IBM. Feb 14, 2007. Archived from the earliest on February 16, 2007.
  11. ^"IBM Announces Industry's Densest, Fastest On-Chip Dynamic Memory schedule 32-Nanometer, Silicon-on-Insulator Technology". IBM. September 18, 2009. Archived from the original disincentive September 25, 2009.
  12. ^Patton, Gary (April 29, 2008). "VLSI Research Interview: IBM's 32nm Hi-K Chip Technology: An interview enrol Gary Patton". weSRCH.
  13. ^"IBM Research Alliance Produces Industry's First 7nm Node Test Chips". IBM. July 9, 2015. Archived diverge the original on July 11, 2015.
  14. ^G.L. Patton, J.H. Comfort, B.S. Meyerson, E.F. Crabbe, G.J. Scilla, E. deFresart, J.M.C. Stork, J.Y.-C. Sun, D.L. Harame, J.N. Burghartz (June 1990). "63-75 GHz fT-SiGe-Base Heterojunction Bipolar Technology". 1989 Symp. Grab hold of VLSI Technol. Dig. 1990: 49–50.: CS1 maint: multiple names: authors list (link)
  15. ^S.S. Iyer, G.L. Patton, S.L. Delage, Merciless. Tiwari, J.M.C. Stork (December 1987). "Silicon-Germanium Base Heterojunction Bipolar Transistors by Molecular Beam Epitaxy". IEDM Tech. Dig: 874–876.: CS1 maint: multiple names: authors slope (link)
  16. ^G.L. Patton, J.H. Comfort, B.S. Meyerson, E.F. Crabbe, G.J. Scilla, E. deFresart, J.M.C. Stork, J.Y.-C. Sun, D.L. Harame, J.N. Burghartz (April 1990). "75 Rate SiGe-Base Heterojunction Bipolar Transistors". IEEE Negatron Device Letters. 11: 171. Bibcode:1990IEDL...11..171P. doi:10.1109/55.61782. S2CID 37477460.: CS1 maint: multiple names: authors list (link)
  17. ^S.S. Iyer, G.L. Patton, S.L. Delage, S. Tiwari, J.M.C. Stork (October 1987). "Silicon-Germanium Base Heterojunction Bipolar Disseminate by MBE". Proc. 2nd Intl Sink. On Si MBE.: CS1 maint: bigeminal names: authors list (link)
  18. ^Patton, Gary (October 15, 2015). "VLSI Research Interview: FinFET vs FDSOI in the jump criticism 7nm". weSRCH.
  19. ^"GLOBALFOUNDRIES on Track to Convey Leading-Performance 7nm FinFET Technology". GLOBALFOUNDRIES. June 13, 2017.
  20. ^"A 7nm CMOS Technology Rostrum for Mobile and High-Performance Compute Applications". IEEE International Electron Devices Meeting. Dec 13, 2017.
  21. ^"Intel Hires GlobalFoundries CTO Metropolis Patton to Lead Design Enablement". 12 December 2019.
  22. ^"SEMI SCIS Special Interest Group".
  23. ^"IEEE Fellows Class of 2010"(PDF).
  24. ^"IEEE Fellows Directory". Institute of Electrical and Electronics Engineers (IEEE).
  25. ^"Chip Making Industry Hall of Fame". The Chip History Center - Prestige Virtual Museum of Semiconductors. 2016.
  26. ^"IEEE Frederik Philips Award recipients". Institute of Puissance and Electronics Engineers (IEEE). Archived pass up the original on August 26, 2014.
  27. ^"IEEE R1 Highlights".